1. Field of the Invention
The present invention relates to shift registers capable of partial driving in which a pulse is generated from several of an entirety of bistable circuits, as well as to display devices using such a shift register.
2. Description of the Related Art
Conventionally, matrix display devices are known in which a plurality of scanning lines and a plurality of signal lines intersect with one another. Known as such matrix display devices are FPDs (flat panel displays) such as LCDs (liquid crystal displays), PDPs (plasma display panels), EL (electronic luminescence) displays, and FEDs (field emission displays). FPDs can be more easily made thinner and lighter than conventional CRTs (cathode ray tubes), so that they are also used in mobile phones. On the other hand, there is a need for lower power consumption in mobile phones. Therefore, there are also display devices provided with a partial display function with which an image is displayed only on a portion of the display screen.
According to the display device disclosed in JP H11-184434A, a partial display can be realized by providing a scan permission signal and masking such that a selection signal is not outputted to the scanning lines corresponding to a non-displayed portion. However, in this case it is necessary to generate a shift clock corresponding to all scanning lines, regardless of the size of the non-displayed portions, and the clock number of the shift clock is the same for full screen display as for partial display. Therefore, the power consumption is not reduced.
To address this problem, a display device provided with storage circuits corresponding to the scanning lines has been proposed, wherein signals for discriminating whether regions are displayed regions or non-displayed regions are held in the storage circuits, and partial display is performed by driving only the scanning lines corresponding to the displayed regions. According to JP 2001-249636A, the plurality of scanning lines provided in this display device are connected to a scanning line driving circuit. Moreover, for partial display, only a portion of the scanning lines are driven by the scanning line driving circuit. In this case, the clock number of the shift clock that is necessary is equivalent to the number of scanning lines corresponding to the display region.
FIGS. 23A, 23B, 24A and 24B are circuit diagrams showing the configuration of a scanning line driving circuit of a conventional display device. The right end of the signal lines shown in FIG. 23A is connected to the left end of the signal lines shown in FIG. 23B. Similarly, the right end of the signal lines shown in FIG. 23B is connected to the left end of the signal lines shown in FIG. 24A, and the right end of the signal lines shown in FIG. 24A is connected to the left end of the signal lines shown in FIG. 24B. This scanning line driving circuit comprises an m-stage shift register consisting of m bistable circuits 101, as well as in D flip-flop circuits 102. The D flip-flop circuits 102 function as storage circuits for discriminating displayed regions and non-displayed regions.
FIG. 25 is a circuit diagram showing the configuration of the bistable circuits of this scanning line driving circuit. This bistable circuit comprises a D flip-flop circuit 201, an OR circuit 202, a combination circuit 203, and an AND circuit 204. The combination circuit 203 is consist of two AND circuits and one OR circuit.
FIGS. 26 and 27 are timing charts of the scanning line driving circuit in the conventional display device during full screen display. The direction of the passage of time is from left to right in FIG. 26, and then from left to right in FIG. 27. Referring to FIGS. 23 to 27, the following is a description of the operation of the scanning line driving circuit during full screen display.
As shown in FIGS. 26 and 27, during the period of full screen display, the logic level of a partial display selection signal PB is kept High. Therefore, the output signal outputted from the OR circuit 202 in FIG. 25 is High, so that the input signal CLRB of the D flip-flop circuit 201 is Low. As a result, the D flip-flop circuit 201 is not reset.
Let us now consider the bistable circuit SR1 of the first stage. After the scanning line driving circuit start signal GSP becomes High, when the pulse of the shift clock GCK is inputted, the D flip-flop circuit 201 is set and the output signal QO (SR1QO) of the bistable circuit SR1 becomes High. Moreover, by setting the input signal OE at High in synchronization with the shift clock GCK, so that the output signal GL that is outputted from the AND circuit 204 becomes High. That is to say, the scanning line of the first stage is driven (i.e. a selection signal whose logic level is High is outputted to the first scanning line).
Let us now consider the bistable circuit SR2 of the second stage. The input signal QI of the bistable circuit SR2 is the output signal QO (SR1QO) of the bistable circuit SR1 of the first stage. Therefore, as shown in FIG. 26, after the output signal QO (SR1QO) of the bistable circuit SR1 of the first stage has become High, when the pulse of the shift clock GCK is inputted, the D flip-flop circuit 201 of the bistable circuit SR2 of the second stage is set. That is to say, due to the same operation as in the above-described bistable circuit SR1 of the first stage, the output signal QO (SR2QO) and the output signal GL of the bistable circuit of the second stage become High. Thus, the second scanning line is driven.
The bistable circuits SR3 to SRm of the third and following stages are operated in a similar manner as the bistable circuit SR2 of the second stage, and all scanning lines are driven sequentially. Thus, full screen display is realized.
The following is a description of the operation of the scanning line driving circuit during partial display. In the conventional display device, first, the settings in the storage circuits for discriminating displayed regions and non-displayed regions are performed. Then, partial display is carried out by sequentially driving the scanning lines with the bistable circuits corresponding to the storage circuits that have been set to indicate the displayed region. The following is a description for the case that the i-th to j-th scanning lines correspond to the displayed region. It should be noted that, as mentioned before, the D flip-flop circuits 102 function as the storage circuits.
FIGS. 28 and 29 are timing charts of the scanning line driving circuit while setting the storage circuits for partial display. The direction of the passage of time is from left to right in FIG. 28, and then from left to right in FIG. 29. Referring to FIGS. 23A, 23B, 24A, 24B, 25, 28 and 29, the following is a description of the operation of the scanning line driving circuit while setting the storage circuits for partial display.
During the period of setting the storage circuits, the partial display selection signal PB is held a High level, and the storage circuit setting clock MCK and MDI are set to High, as shown in FIG. 28. Here, every time a pulse of the storage circuit setting clock MCK is inputted, the output signals Q of the D flip-flop circuits 102 are inputted as the input signal D into the D flip-flop circuit of the next stage. For this reason, by setting MDI to High as shown in FIG. 28, the D flip-flop circuits DFFi to DFFj of the i-th to the j-th stage are set.
FIGS. 30 and 31 are timing charts of the scanning line driving circuit during partial display. The direction of the passage of time is from left to right in FIG. 30, and then from left to right in FIG. 31. Referring to FIGS. 23A, 23B, 24A, 24B, 25, 30 and 31, the following is a description of the operation of the scanning line driving circuit during partial display.
When the setting of the storage circuits for partial display as described above has finished, the logic level of the partial display selection signal PB is held at Low, as shown in FIGS. 30 and 31. Here, when the scanning line driving circuit start signal GSP is set to High, the output signal QO (SR1QO to SRi-1QO) of the bistable circuits SRQ to SRi−1 of the first to (i−1)-th stage become High. After this, the partial display begins when a pulse of the shift clock GCK is inputted.
In the bistable circuit SRi of the i-th stage, the output signal GL (GLi) that is outputted from the AND circuit 204 and the output signal QO (SRiQO) that is outputted from the combination circuit 203 become High.
In the bistable circuit SRi+1 of the (i+1)-th stage, the input signal QI is the output signal QO of the bistable circuit SRi of the i-th stage, so that when the pulse of the shift clock GCK that is marked “i+1” in FIG. 30 is inputted, the output signal GL (GLi+1) of the bistable circuit SRi+1 of the (i+1)-th stage becomes High. Also for the bistable circuits SRi+2 to SRj of the (i+2)-th to the j-th stage, the same operation as for the bistable circuit SRi+1 of the (i+1)-th stage is performed. As noted above, the output signals GL (GLi to GLj) of the bistable circuits SRi to SRj of the i-th to j-th stage sequentially become High. That is to say, the scanning lines of the i-th to the j-th stage are driven sequentially, and partial display is performed.
With the conventional art as described above, in order to distinguish between bistable circuits driving a signal line and bistable circuits not driving a signal line, a corresponding storage circuit is necessary for each of the bistable circuits within the shift register, so that there is the problem that the circuitry increases in scale. Moreover, when the circuitry increases in scale, the power consumption increases, posing the problem of how to decrease the power consumption.